The concept introduction discusses the classic RISC pipeline used in early reduced instruction set computer central processing units (RISC CPUs) such as MIPS, SPARC, Motorola 88000, and DLX. These CPUs employ a five-stage execution instruction pipeline where each stage works on one instruction at a time, using flip-flops to hold state and combinational logic for processing.
UC Berkeley
Fall 2022
This course deepens students' understanding of computer architecture and the translation of high-level programs into machine language. Emphasis is on C and assembly language programming, computer organization, parallelism, CPU design, and warehouse-scale computing. Prerequisites include CS61A and CS61B or equivalent C-based programming experience.
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